Field-programmable gate array

Results: 1389



#Item
751Electronic engineering / Engineering / Telecommunications engineering / CYPRIS / Field-programmable gate array / SPIE / Communications security

Space Programmable INFOSEC Engine (SPIE) Multi-purpose Radiation Hardened Processor A Member of the General Dynamics Family of Advanced Core Cryptographic

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Source URL: www.gdc4s.com

Language: English - Date: 2014-12-04 04:05:04
752Embedded system / Field-programmable gate array / Scalability / Operating system / Computer / Distributed computing architecture / Cloud computing / Reconfigurable computing / Computing / Electronics / Technology

Today, you have the golden opportunity to witness first hand an actual DARPA experiment!! Me! I am a new official "experimental employee" fully approved and mandated by Congress under section 1101 of the Strom Thurmond N

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Source URL: archive.darpa.mil

Language: English - Date: 2000-11-17 15:49:10
753Fabless semiconductor companies / Electronics manufacturing / Field-programmable gate array / Prognostics / Altera / Built-in self-test / Ball grid array / Semiconductor intellectual property core / Solder / Electronic engineering / Electronics / Electromagnetism

FOR IMMEDIATE RELEASE Ridgetop Group, Inc[removed]North Oracle Road Tucson, AZ[removed]Phone: [removed]

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Source URL: www.ridgetopgroup.com

Language: English - Date: 2011-02-11 12:03:40
754Nios II / Embedded operating systems / Real-time operating systems / Field-programmable gate array / Sopc builder / Altera / Nios embedded processor / Joint Test Action Group / Trivial File Transfer Protocol / Software / Computing / Electronics

AN 429: Remote Configuration Over Ethernet with the Nios II Processor

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Source URL: www.altera.com

Language: English
755Formal methods / Electronic design automation / Field-programmable gate array / Statistical static timing analysis / Static timing analysis / Standard cell / Application-specific integrated circuit / Integrated circuit design / Pattern matching / Electronic engineering / Electronics / Integrated circuits

Accelerating Monte Carlo based SSTA Using FPGA Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan and Yi Zou Computer Science Department, University of California, Los Angeles Los Angeles, CA 9009

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Source URL: cadlab.cs.ucla.edu

Language: English - Date: 2010-02-11 21:54:56
756Fabless semiconductor companies / Joint Test Action Group / Manufacturing / Altera / SiliconBlue Technologies / Electronic engineering / Electronics / Field-programmable gate array

AlteraIllustratorTemplate

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Source URL: www.altera.com

Language: English - Date: 2014-09-08 21:56:13
757Computer buses / Integrated circuits / Electronics manufacturing / Joint Test Action Group / Altera / Universal Serial Bus / Field-programmable gate array / Nios II / Programmer / Computer hardware / Electronic engineering / Electronics

Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices

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Source URL: www.altera.com

Language: English - Date: 2014-08-15 04:44:34
758Electronic engineering / Joint Test Action Group / Boundary scan / Altera / Field-programmable gate array / Shift register / Boundary scan description language / Serial Vector Format / Electronics manufacturing / Manufacturing / Electronics

AN 39: IEEE[removed]JTAG Boundary-Scan Testing in Altera Devices

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Source URL: www.altera.com

Language: English - Date: 2010-05-05 19:29:24
759Fabless semiconductor companies / Field-programmable gate array / Jason Cong / Logic synthesis / Altera / Application-specific integrated circuit / Special Interest Group on Design Automation / Computing with Memory / Synplicity / Electronic engineering / Electronics / Digital electronics

Microsoft Word - resume10.doc

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Source URL: cadlab.cs.ucla.edu

Language: English - Date: 2010-03-01 17:23:10
760Digital electronics / Electronic design / Integrated circuits / Field-programmable gate array / Logic synthesis / Xilinx / Logic optimization / Jason Cong / Algorithm / Electronic engineering / Electronics / Electronic design automation

230 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 Optimality Study of Logic Synthesis for LUT-Based FPGAs

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Source URL: cadlab.cs.ucla.edu

Language: English - Date: 2007-01-18 13:56:58
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